A technology has been known, which reads failure information from a RAM (random access memory) provided in a system and analyzes the failure information when a failure occurs in the system. Further, a method of estimating a failure causing location by analyzing the failure information (Fault Location) has been known.
The method of estimating the failure causing location will be described by using FIG. 9. FIG. 9 is a diagram illustrating a hardware configuration of a system in the related art. Herein, a system 200 includes a CPU (central processing unit) 210, a chip set 220, PCI (peripheral component interconnect)-Express switches (hereinafter, may be simply referred to as switches) 230 to 235, and a PCI-Card 240. The switch 230 is connected to communicate with the switch 231 and the switch 232 through a PCI-Express bus and the switch 233 is connected to the switch 234 and the switch 235 through the PCI-Express bus. Further, the chip set 220 is connected to communicate with the switch 230 and the switch 233 through the PCI-Express bus. In addition, the PCI-Card 240 is connected to each of the switches 231, 232, 234, and 235 through the PCI-Express bus.
In the system 200 configured as above, for example, when a failure occurs in the switch 232, the chip set 220 notifies the occurrence of the failure by interrupting the CPU 210. The CPU 210 is interrupted by the chip set 220 to detect that the failure occurs in the system 200. Further, when the CPU 210 detects that the failure occurs, the CPU 210 reads respective registers of the chip set 220, the switches 230 to 235, and the PCI-Card 240, analyzes a cause of the failure, and estimates a failure causing location, through the PCI-Express bus.
However, a state in which the register is not able to be read (master abort) may occur due to various causes such as link breakage of the PCI-Express bus or hang of a PCI-Express transmission/reception buffer. FIG. 10 is a diagram for describing a case in which the register is not able to be read.
As illustrated in FIG. 10, for example, when link breakage occurs in the PCI-Express bus between the chip set 220 and the switch 230, the CPU 210 is not able to read the respective registers of the switches 230 to 232 or the PCI-Card 240 connected to the switches 231 and 232.
Therefore, the failure causing location is not able to be estimated in detail, and for example, in order to remove the failure, all components of the switches 230 to 232 and the PCI-Card 240 connected to the switches 231 and 232 are to be replaced.
That is, when master abort occurred, a failure causing location is not able to be estimated in detail.
Patent Document 1: Japanese Laid-open Patent Publication No. 05-282167